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Entry type: FAQ Entry ID: 18325417, Entry date: 07/25/2011
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Where and when do you need peripheral addressing?

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Description If access is made to the inputs and outputs via the operands 'I...' or 'Q...' in the user program, then there is no direct access to the input/output modules. In this case, access is made to a memory area in the CPU's system memory. This area is called the process image of the inputs (PII) and the process image of the outputs (PIQ). The contents of the process image (PII and PIQ) do not reflect the actual values of the inputs/outputs, but th ...

Description
If access is made to the inputs and outputs via the operands "I..." or "Q..." in the user program, then there is no direct access to the input/output modules. In this case, access is made to a memory area in the CPU's system memory. This area is called the process image of the inputs (PII) and the process image of the outputs (PIQ). The contents of the process image (PII and PIQ) do not reflect the actual values of the inputs/outputs, but the values at the time the process image was updated. If more recent values are required for individual processes, you also have the option of direct peripheral addressing.
You can also assign I/O addresses outside the process image to the inputs and outputs of I/O modules. But then these I/O addresses must be accessed via "Peripheral addressing". For the sake of clarity, this entry will first describe the different types of process image and then the "Peripheral addressing".

The OB1 process image
The OB1 process image (OB1-PI) can be used in any CPU. It is updated cyclically before the OB1 is processed. The program is processed cyclically in the following order:

  1. Processing of internal jobs of the CPU's operating system.
  2. Writing of states from the OB1 process image of the outputs to the outputs of the modules.
  3. Reading of the input states from the modules into the OB1 process image of the inputs.
  4. Processing of the user program in OB1.
  5. Continue with Step 1.

The operating system automatically executes the writing and reading of the OB1 process image (OB1-PI). With S7-400 CPUs you can also disable the cyclic updating of the OB1 process image ("HW Config" > "Object Properties"[CPU] > "Cycle/Clock bit memory" > "Update OB1 process image cyclically"). You can then update the OB1 process image in the user program with SFC 26 (UPDAT_PI) and SFC 27 (UPDAT_PO).

The following holds generally for cyclic updating of the OB1 process image:

  • The shorter the cycle time, the more frequently the OB1 process image is updated.
  • The time it takes to update the process image depends on the plant concerned in each case. Factors of influence here:
  • The number of individual modules that have to be read from or written to.
  • The baud rate of communication with the individual modules.
  • The protocols used for addressing the individual modules (MPI, PROFIBUS, ...).
  • If the OB1 process image is enlarged (not possible with all CPUs), then the cycle can also be extended if this means that there are more modules in the process image.

Process image partitions (PIP)
In addition to the OB1 process image, in some types of CPU you also have the option of using process image partitions (PIP). You can assign I/O address areas of the modules to these process image partitions. Each address area can either be assigned to the OB1 process image or to a process image partition. Multiple assignments are not possible.
The process image partitions can be updated in two different ways:

  • in the user program via SFC 26 (UPDAT_PI) and SFC 27 (UPDAT_PO),
  • by assigning a PIP to an OB.

During updating with an SFC, the read/written data of the process image partitions is consistent up to a certain data length depending on the CPU. Information on this is available in the S7 Online Help for the SFC.

The assignment of a process image partition to an OB for updating can be parameterized in the hardware configuration ("Object Properties" [CPU] > "Cycle/Clock bit memory"). There you can assign exactly one process image partition to individual OBs. Depending on the OB, the input values of the assigned process image partition are read in when the OB is called. The output values of the assigned process image partition are written to the outputs immediately after the OB has been processed. For this please refer to the Online Help for the OB concerned (process image partitions that are assigned to OBs 61 to 64 are not updated automatically).

"Peripheral addressing"
The process image often does not comprise the whole I/O address area of the CPU. So, for example, CPU315-2DP (6ES7315-2EG10-0AB0) has a total I/O address area of max. 2048 bytes of inputs/outputs, but only a fixed process image of 128 bytes.
If I/O address areas of a module are outside the process image, you must access these areas via "Peripheral addressing". The peripheral addresses are accessed immediately after addressing the addresses in the user program. Thus with "Peripheral addressing" it is always ensured that the actual value is read in immediately or an output is implemented immediately. This is particularly important for analog values and process alarms.
Via "Peripheral addressing" you can also access modules whose I/O address areas are assigned to a process image.
"Peripheral addressing" also means that the modules can be accessed directly. For this you set a "P" in front of the area of the address to be addressed:

  • PIB --> Peripheral Input Byte
  • PQB --> Peripheral output Byte
  • PIW --> Peripheral Input Word
  • PQW --> Peripheral output Word
  • PID --> Peripheral Input Double-word
  • PQD --> Peripheral Output Double-word

You can use "Peripheral addressing" if

  • The address areas of modules are not assigned to any address image.
  • In the control program you need input values that are more recent than those available in the process image.
  • Output values are to be written as quickly as possible to the outputs (at least one byte).

Note the following points when for "Peripheral addressing":

  1. Direct access to a peripheral address involves a much higher access time than access to the process image.

    Example:

CPU 317-2 DP: L   IB    x        0.05 μs
  L   PIB x      15.01 μs
  • The values that are read with the two instructions "L PIB 1" and "L PIW 2", for example, are not consistent. However, the values are consistent if they are read in via "L PID 1". If larger contiguous input areas (> 4 bytes) are to be read directly and consistently, then you can use SFC 14 (DPRD_DAT). If larger contiguous input areas (> 4 bytes) are to be written directly and consistently, then you can use SFC 15 (DPWR_DAT).
     
  • You cannot address any individual "peripheral bits". Direct writing/reading of the peripheral must always be done byte for byte. However, here you can benefit from the fact that in the case of direct write access to peripheral outputs that are in the PA area of the CPU, the process image of the outputs follows suit.

Example:


Fig. 01

  • In the above operation A Q 1.0, the signal state of output Q 1.0  already corresponds to that which has been assigned to the relevant bit in the output byte AB 1 with the previous direct peripheral access.
    In the case of a direct read access to peripheral inputs that are in the PQ area of the CPU, the process image can be updated via load and transfer commands.

Example:


Fig. 02

The operand areas I and Q of the process image can be edited at will through MC7 commands and can thus be used as "storage area" for the further processing and preprocessing of peripheral signals. Of course, you can also use other operand areas such as M, D or L.

  • You can only have read-only access to the input addresses.
  • You can only have write-only access to the output addresses.

More information about possible operations is available in the instruction lists for the CPUs:

  • SIMATIC S7-300 CPUs:
    "Operation list S7-300 CPU312 IFM, CPU313, CPU314, CPU314 IFM, CPU315, CPU315-2 DP, CPU316-2 DP, CPU318-2" in Entry ID: 8861817.
    "Operation list S7-300 CPU 312, CPU 314, CPU 315-2 DP, CPU 315-2 PN/DP, CPU 317-2 PN/DP, CPU 319-3 PN/DP, IM 151-8 PN/DP CPU, IM 154-8 PN/DP CPU" in Entry ID: 31977679.
  • SIMATIC S7-400 CPUs:
    "Operation list S7-400 CPU 412, 414, 416, 417" in Entry ID: 23904435.
    "Operation list S7-400 CPU 412-2 PN, CPU 414-3 PN/DP, CPU 414F-3 PN/DP, CPU 416-3 PN/DP, CPU 416F-3 PN/DP" in Entry ID: 44395684.

The current size of the process image of the CPU implemented is available online via "PLC > Diagnostics/Settings > Module Status > Performance data". Depending on the type of CPU, you can also make the process image larger or smaller in the hardware configuration ("Object Properties"[CPU] > "Cycle/Clock marker"). More information on the size of the process image and on the peripheral address area is available in the following manuals:

  • SIMATIC S7-300 CPUs
    "S7-300 CPU 31xC and CPU 31x, Technical Data" in Entry ID: 12996906 in Chapters 6 and 8.
  • SIMATIC S7-400 CPUs:
    "Automation System S7-400 CPU Specifications" in Entry ID: 14016796 in Chapter 6.
    "S7-400 Automation System, CPU Specifications" in Entry ID: 23904550 and 44444467 in each case Chapter 10.

The maximum size of the process image specified in the technical data refers to the size of all the process images together (OB1-PQ and all the PIPs for inputs and outputs). The smallest address for the process image is the address "0", whilst the largest address is the "size of the process image" minus 1.

Notes on the IM 151-7 CPU
With free addressing

  • The selection of the input and output addresses of modules can be byte granular and separate from each other.
  • If bit-granular addressing is not possible, compression of digital channels is not supported.

Thus it is not possible to "pack" addresses. The bits of a byte possibly released with byte-granular addressing cannot be occupied in the user program.

Note on S7-400H CPUs
Additional synchronization is required in the case of peripheral access to S7-400H CPUs, resulting in a higher processing time.

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