Entry type: FAQ, Entry ID: 54647747, Entry date: 03/27/2013

How do you program a pulse encoder in STEP 7 (TIA Portal)?

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Alternative 1
You can simply program a pulse encoder using the IEC times of STEP 7 (TIA Portal). Fig. 01 shows the interconnection of the two "TON" instructions (generate switch-on delay) in order to receive a periodic output signal at output A0.1.

Fig. 01

The "Generate switch-on delay" instructions delay the setting of outputs Q by the programmed time PT. The table below explains the function of the pulse encoder.

No. Function of the pulse encoder
1 The input E0.0 "Release" triggers the pulse encoder.
2 To begin with the marker M0.1 "Out" has the "False" signal so that the time period of the switch-on delay of the lower "TON" instruction is started.
3 When the switch-on delay expires the marker M0.0 "Trig" is set and
  • the output A0.1 "Trig_Out" receives the "True" signal.
4 The "True" signal at marker M0.0 triggers the time period of the switch-on delay of the upper "TON" instruction.
5 When the second switch-on delay expires the marker M0.1 "Out" is set.
6 The "True" signal at marker M0.1 opens the opener and interrupts the lower "TON" instruction which resets the marker "M0.0".
  • The output A0.1 "Trig_Out" receives the "False" signal.
7 The "False" signal at marker M0.0 interrupts the upper "TON" instruction and the marker M0.1 is reset.
8 The "False" signal at marker M0.1 retriggers the lower "TON" instruction and the process starts from the beginning again.
Table 01

Fig 02 shows the pulse diagram of the pulse encoder.

Fig. 02

More information about the IEC timer instructions is available in the STEP 7 (TIA Portal) Online Help. For this you mark the instruction and press the "F1" key.

Alternative 2
You can periodically change the binary statuses in the pulse-pause ratio of 1:1 by configuring clock markers.

No. Procedure
1 Open the device configuration in your STEP 7 project and double-click the S7 CPU module in the Device View.
2 Select the "Properties" tab and click "System and clock memory" in the area navigation.
3 Enable the "Enable the use of clock memory byte" option and enter an address for the clock marker byte; for example, "100" for MB100. This assigns a frequency to each bit of this clock marker byte.

Fig. 03

4 Save and compile the hardware configuration. Then load your program onto the CPU.
5 The frequency of 10Hz is assigned to the marker M100.0 and thus its binary status changes every 0.1 seconds. Fig. 04 shows an example of periodic increment of the value for the operand MD110 at the "IN/OUT" parameter. The link of the comparator with the MOVE instruction limits the value for the operand to 99 and then resets it to 0.

Fig. 04

Table 02

Advantages of Alternative 1

  • The times for the pulse lengths of the True and False signal can be variable.
  • In this way you can also program the pulse-pause ratio flexibly.

Advantages of Alternative 2

  • Little effort required for configuration.
  • You do not need the IEC timer instructions.

Notes on using clock markers
A clock marker is a marker that changes its binary status periodically in the pulse-pause ratio of 1:1. Since the marker cycle runs asynchronously to the CPU cycle, in long cycles the status of the clock marker can change several times, which leads to distorted perception.


  • A clock marker has a period time of 100ms.
  • The cycle time of the program is 100ms and fluctuates by between plus to minus 10ms.
  • If the clock marker has the status 1 after several periods, you might get the impression when monitoring that its status does not change around 300ms.

Fig. 05

1) Clock marker changes every 100ms
2) Cycle time: 110ms
3) Cycle time: 90ms
4) Online monitoring of the clock marker

The download includes a STEP 7 (TIA Portal) program for the S7-1200 modules, which you can use to generate pulses from the clock marker byte. The edge bits are formed initially byte by byte and then assigned to the outputs bit for bit. You need the following for bit-for-bit and symbolic access to tags of the Byte, Word or DWord data types:

  • STEP 7 V11+SP1+Update 2 (or higher)
  • and for the S7-1200 modules the firmware version V2.0 (or higher).

Copy the "STEP7_V11_Slice_Takt.zip" file into a separate directory and then start the file with a double-click. The STEP 7 TIA Portal project is now unpacked automatically with all the associated subdirectories. You can then use STEP 7 TIA Portal to open and process the extracted project.

STEP7_V11_Slice_Takt.zip ( 3369 KB )

Creation environment
The pictures and download in this FAQ were created with STEP 7 V11.0+SP1.