Entry type: Download, Entry ID: 6741018, Entry date: 08/20/2014
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Operating System Updates V3-H and V1-H CPU414-4H / CPU417-4H

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  • Associated product(s)
Firmware Download S7-400 H-CPUs V3 und V1

In this entry, you will find the firmware versions for the following S7-400 CPUs:

  • 6ES7414-4HJ00-0AB0
  • 6ES7417-4HL00-0AB0
  • 6ES7417-4HL01-0AB0

The current firmware version of H-CPU V6.0 see: 109474550

  • 6ES7 412-5HK06-0AB0
  • 6ES7 414-5HM06-0AB0
  • 6ES7 416-5HS06-0AB0
  • 6ES7 417-5HT06-0AB0

The current firmware version of H-CPU V4.5 see: 109474703

  • 6ES7 412-3HJ14-0AB0
  • 6ES7 414-4HM14-0AB0
  • 6ES7 414-4HR14-0AB0
  • 6ES7 417-4HT14-0AB0

The current firmware version of H-CPU V4.0 see: 109474747

  • 6ES7 414-4HJ04-0AB0
  • 6ES7 417-4HL04-0AB0

The latest firmware is located at the end of the entry.

 

General information about the firmware update

When firmware is updated, it must always be updated to the latest version available for the relevant MLFB. The previous versions of the firmware are only intended as a backup to enable you to downgrade to the original version, although this has never been known to be necessary.

The latest version of CPU firmware in each case is valid for all revision levels of this MLFB.

The CPU undergoes a general reset after a firmware update.

 

FW Update for Firmware V3 and V2
Whether an update to a new firmware version can be performed depends on the affected production facility, since an update is only possible, if the facility is turned off.   
An update of the H system to the latest firmware version is only possible while the facility is off.

Downgrading to an older Firmware Version
In the case of a CPU417-4H (order number 6ES7 417-4HL01-0AB0) with a test date of R, S or T, a downgrade can only be performed down to and including V3.0.0. The test date can be identified by the yellow test sticker on the back of the module. The test date is on the second line below SIEMENS/TESTED and following VP.
If a downgrade is desired and the above restriction applies, please contact your local Siemens office.

Should you encounter Problems during the Firmware Update ...
CPUs delivered during a particular delivery period can exhibit problems during the firmware update. 

These CPUs can be identified by one of the following error patterns:

  • All LEDs permanently remain lit, i.e., for longer than the normal update process of up to approx. 4 minutes
  • The LEDs INTF and EXTF blink 

Should you encounter one of the above problems, an error correction is available.

Prerequisites for the Creation of an Operating System Update Card

  • S7 memory card
     Flash 4 MB (order number 6ES7 952-1KM00-0AA0) or higher 
  • STEP 7 V3.1 or higher
  • PG or PC with external prommer for programming the memory card 

Prerequisites for the Creation of an Operating System Update Card

  • S7 memory card
    Operating system version < V4.5.0: Flash 4 MB (order number 6ES7 952-1KM00-0AA0) or higher
    Operating system version >= V4.5.0: Flash 8 MB (order number 6ES7 952-1KP00-0AA0) or higher
  • STEP 7 V3.1 or higher
  • PG or PC with external prommer for programming the memory card 

General procedure for updating the Operating System

  • Power off the power supply (PS) of the rack in which the CPU is inserted
  • Insert the prepared operating system update card into the CPU
  • Power ON the power supply (PS) of the rack in which the CPU is inserted
  • The operating system is transferred from the memory card to the internal FLASH EPROM; during this process, all indicator LEDs on the CPU are lit (INTF, EXTF, FRCE, CRST, RUN, STOP). The operating system update will take approx. 2 minutes; completion is indicated by the STOP LED at the CPU flashing slowly => prompt by the system for overall reset.
    CAUTION:
    Immediately following the update, a self-test is started, which takes a few minutes depending on the memory size. 
  • Power off the power supply (PS) and if necessary insert the memory card intended for operations
  • Power on the power supply (PS); the CPU automatically performs an overall reset and is then immediately operational
  • After a successful operating system update please set the time

Information on Parts Replacement

In an S7-400H system, both CPUs must have the same firmware version. If one CPU of your S7-400H fails, order a new CPU with exactly the same order number. It will be delivered with the latest firmware version.
Further action depends on whether the system must continue to run without interruption or whether it can be stopped briefly. If stopping the system is not permissible, then the newly obtained CPU must be downgraded to the firmware version of the CPU still running. In that case, proceed as follows:

  • Create an operating system update card containing the firmware version of the failed CPU
  • Use this card to transfer the firmware version of the failed CPU to the new CPU
  • Both CPUs now have the original firmware version; your S7-400H can now be switched to the redundant operating mode 

If an overall stop of the system can be tolerated, the existing CPU can be updated to the latest version by stopping the system.

Difference of this Operating System Update compared to the other S7-400 CPUs

Following the actual firmware update, a self-test will start with the H system. This can take several minutes depending on the size of the load memory (size of the memory card inserted) and the size of the main memory.  

 

Error correction in the case of problems with the operating system update

1. Affected CPUs

6ES7 414-4HJ00-0AB0HW Release: 1
6ES7 417-4HL01-0AB0 HW Release: 1

 (The HW release can be read via: STEP 7 / Target System / Module Status Tab: General)

CPUs manufactured in the time frame from June 02 to September 02 are affected, which can be identified by the yellow test sticker on the back of the CPU.
The following identifiers correspond to the above time frame: VPP6, VPP7, VPP8, VPP9  

2. Corrected CPUs

Corrected CPUs (except CPU41x-4H) can be identified by their newer HW release:

6ES7 414-4HJ00-0AB0HW Release: 1 (*)
6ES7 417-4HL01-0AB0HW Release: 1 (*)

(*) HW release not be incremented after error correction

3. Performing the Error Correction
The error correction is performed similarly to an operating system update. At first, a memory card containing the error correction is created by means of STEP 7. The contents of this memory card is then transferred to the CPU.
In H systems as well, this error correction can only be carried out with the CPU switched off, and should therefore be performed in the context of the operating system update.

Prerequisites for the Creation of a Memory Card for the Error Correction:

  • S7 memory card of the type: Flash with at least 2 MB (also with CPU41x-4H)
  • STEP 7 V3.2 or higher
  • PG or PC with external prommer for programming the memory card   

Creating a Memory Card for the Error Correction:

  1. Download the file:    update_v145.exe (315,2 KB)
  2. Unpack the file by double-clicking on the file name 
  3. In the SIMATIC Manager, erase the memory card by means of "File / S7 Memory Card / Delete"
  4. Program the memory card by selecting "Target System / Update Operating System" in the SIMATIC Manager and selecting the target folder; start the programming process by opening the file "CPU_HD.UPD".
  5. The memory card has been programmed once the default mouse pointer reappears. With newer STEP 7 versions, a corresponding message will appear.

Transfer to the CPU: 

Important: The loading process must not be interrupted (e.g., by a power off/on).
The loading process cannot be repeated after an interruption. In such a case, the CPU must be returned to the factory for repair.

  1. Power off the power supply (PS) of the rack in which the CPU is inserted 
  2. Insert the prepared memory card into the CPU 
  3. Permanently hold the key switch of the CPU in the position MRES
  4. Power ON the power supply (PS) of the rack in which the CPU is inserted; after approx. 10 s, the LEDs INTF / FRCE / RUN / STOP will start flashing  
  5. Briefly release the key switch (< 3 s), briefly return to MRES and then release again
  6. The loading process will start:
    LED INTF: Continuously lit - rapid flashing - continuously lit again 
  7. The loading process has been successfully completed once the LED EXTF remains continuously lit (after approx. 15 s) 
    If an error occurred during the loading process, it can be identified as follows:
    - LED FRCE continuously lit => the CPU is not affected by this error 
       (or the error correction has already been performed)
    - Rapid flashing of the LEDs INTF and EXTF => internal error; the module has to be returned for repairs 
    - Slow flashing of the LED INTF => the memory card is not functional
  8. Afterward, perform the operating system update. 

 

 

 

Update V1.1.0 (Backup)

 

Files for firmware version

 
 MLFB 
 V1.1.0 
 CPU 417-4HL00 6ES7 417-4HL00-0AB0

  a174hl00.exe (803,8 KB) 

 

 

 

 

 

Update V2.1.0 (Backup)

Functional Enhancements:

  • Configuration changes in RUN mode
  • Connecting/updating without disconnection
  • Significant improvement of the runtimes with communications functions
  • Operation in a standard station
  • Connection diagnostics (system status list 0x36H)
  • With 6ES7 417-4HL01-0AB00, there is a larger internal memory to avoid communications bottlenecks

Product Information Firmware V 2.1.0:   pi417_4h.pdf (64,3 KB)

Files for firmware version

 
 MLFB 
 V2.1.0 
 CPU 417-4HL00 6ES7 417-4HL00-0AB0  b174hl00.exe (920,0 KB)

 

 

 

Update V2.1.1 (Backup)

The following errors were eliminated for CPU 417H:

  • When connecting/updating with memory expansion, it could happen that even before the update trigger, the inputs/outputs had not been updated for several seconds.
  • With one-sided I/O in rack 1 of the H system, the following situation could occur: If there was a fault in an output module, which resulted in I/O area access errors (I/O AAE), then I/O AAE was also issued for slot 1 of station 1 (smallest address).
  • By reading the diagnostics buffer about the communication, in extremely rare cases there could be loss of redundancy (stop of the standby) with the event ID 7323, if many new entries were created at the same time the diagnostics buffer was read.
  • In the case of systems with F components, connecting/updating could cause the CPU A (see below) to be switched to the STOP operating mode by F drivers shortly after the switchover process. The conditions were:
    - CPU A was at least 1 minute in RUN mode
    - With CPU A, the last POWER ON must have occurred at least 5 seconds sooner than that of CPU B
    - CPU A performs an update of CPU B

Product Information Firmware V 2.1.1:   pi41x_4h.pdf (103,8 KB)

Files for firmware version

 
 MLFB 
 V2.1.1 
 CPU 414-4HJ00 6ES7 414-4HJ00-0AB0  c144hj00.exe (930,6 KB)
 CPU 417-4HL00 6ES7 417-4HL00-0AB0  c174hl00.exe (921,3 KB)
 CPU 417-4HL01 6ES7 417-4HL01-0AB0  c174hl01.exe (921,3 KB)

 

 

 

Update V2.1.2 (Backup)

The following errors were eliminated for CPU 414H:

  • With firmware versions lower than V2.1.2, calling the SFC87 "C_DIAG" could cause the input I 38.0 to be changed.
  • Contrary to the information in the current Online Help pertaining to system function / function blocks, the following applies when calling SFC51 "RDSYSST" with SZL_ID:=W#16#0112 and INDEX:=W#16#0400: The characteristic ID W#16#0401 is reserved for the operating system. The (new) characteristic ID W#16#0403 indicates that the SFC87 is available on your CPU

Product Information Firmware V 2.1.2:   product information.pdf ( 104 KB )

Files for firmware version

 
 MLFB 
 V2.1.2 
 CPU 414-4HJ00 6ES7 414-4HJ00-0AB0  d144hj00.exe (930,6 KB)
 CPU 417-4HL00 6ES7 417-4HL00-0AB0  d174hl00.exe (931,3 KB)
 CPU 417-4HL01 6ES7 417-4HL01-0AB0  d174hl01.exe (931,3 KB)

 

 

 

 

Update V2.1.3 (Backup) 

The following errors have been corrected with Operating System V2.1.3:

  • In the case of S7-400 CPUs, the EXTF LED did not reset in certain circumstances after a failure of the battery backup. This has been corrected.
  • With S7-400 CPUs, a successful operating system update is now entered correctly in the diagnostics buffer.
  • Incorrect values in the SZL424 (operating status) immediately after the status transition have been eliminated.
  • In the 8x mode of the SFC39, only the "Substitute Event" w#16#5380 and no longer the OB start event is entered.
  • In certain cases, when operating flash memory cards in the CPU, it was necessary to perform a power off/on of the CPU after loading the STEP 7 project, because the CPU reported a parameterization error with startup fault. This has been corrected.
  • In the case of error event 6547 "Parameterization Error when assigning Parameters to K Bus Modules", the module rack number and slot of the DP master are specified in the detailed information of the event, because the master system ID cannot always be determined upon the error detection. It is likewise possible for inserted sub-modules to display the number of the interface module.
  • The cyclic self-test has been extended so that sporadic checksum errors are recognized and corrected before they take effect.
  • If the geographical address of a connected slave was determined in the H system, both master system IDs from CPU Rack 0 and CPU Rack 1 were provided, which could lead to synchronization errors.
  • If HMI systems are linked, many screen tags are updated and single-sided events (e.g., alarms and communication functions) occurred in a very small time window, the result could be a sporadic loss of synchronization.

Product Information Firmware V 2.1.3:   Product informationV213_H.pdf ( 81 KB )

Files for firmware version

 
 MLFB 
 V2.1.3 
 CPU 417-4HL00 6ES7 417-4HL00-0AB0  e7_4hl00.exe (950,5 KB)

 

 

 

Update V2.1.4 (Backup)

The following errors have been corrected with Operating System V2.1.4:

  • In an H system, central expansion units are attached to master and standby. If the voltage supply of the central expansion units breaks down at both the master and standby within approx. 4 ms, a synchronization error might occur after the voltage returns.
  • After numerous connection faults within short periods of time (e.g., several power off cycles), the CPU - in rare cases - entered the DEFECT mode.
  • A large number of monitoring tasks carried out simultaneously (same cycle) by an OS system could - in very rare cases - lead to a loss of synchronization loss in the H system. 
  • In V2.1.3, it was not possible to read out the time remaining of an activated (not yet started) time delay interrupt via SZL 0x222.
  • If a simplex I/O is assigned to rack 0 of an H system, DEFECT mode may occur in rack 1 when loading a configuration to the CPU.
  • The EXTF LED of the CPU remained lit and did not go out after a power off/on cycle or after the return of a DP standard slave (see FAQ 9824085).

Product Information Firmware V 2.1.4:   A5E130864.pdf ( 72 KB )     

Files for firmware version

 
 MLFB 
 V2.1.4 
 CPU 417-4HL00 6ES7 417-4HL00-0AB0  f7_4hl00.exe (952,2 KB)

 

 

Update V2.1.5 (recommended for upgrading)

The following errors have been corrected in V2.1.5:

  • Under certain circumstances, a defect could occur in the CPU, whereby the diagnostics buffer would not contain a corresponding (defect) entry after a power off/on cycle.

  • When switching off the supply voltage to the last PROFIBUS DP station of a line (with bus terminating resistor), a loss of synchronization with the event ID 43DA could occur.

  • After repeated power off/on cycles, a PROFIBUS DP slave (according to EN 50170) would no longer be correctly accepted.

  • In an H system coupled with an APPLICOM PCI Ethernet module, the following defect could occur: 4550 / b003 / 8752 / 01ae

  • If the communication load is high and several cyclic HMI tasks have to be executed at the same time, a loss of synchronization could occur in very rare cases.

Product information A5E000130864_03:  A5E1130864_03.pdf ( 72 KB )

Files for firmware version

 
 MLFB 
 V2.1.5 
 CPU 417-4HL00 6ES7 417-4HL00-0AB0  4174hl00_v215.exe (1020,2 KB)

 

 

 

Update V3.0.0 (Backup)

New functions available with V3.0 for all S7-400 CPUs.

 

Full DP V1 integration in compliance with PROFIBUS standard IEC 61158 Part 3-6, compatible with existing devices.

 

Advantages of this functionality:

  • DP V1 slaves can report quickly to the S7-400 by alarm.
  • This improves the distributed diagnostics performance for DP V1 slaves.
  • Extended parameterization options through data record services. This also permits intelligent field devices to be configured.
  • Many features that previously were only possible with S7 slaves will in the future also be open to other DP manufacturers.
  • Alarms in every operating mode, with new alarm OBs such as status alarm, update alarm and manufacturer-specific alarm.

Further Information on the DP V1 Integration
Descriptions and information on switching from PROFIBUS DP to PROFIBUS DPV1 can be found in entry ID 7027576; information on new OBs/SFBs in connection with DPV1 can be found in entry ID 1214574

Functional enhancements available with V3.0 for all CPUs mentioned above:

  • Time synchronization with status also via PROFIBUS DP interface.
  • Runtime improvement for connection-based master-slave communication.
  • Setting the time and time status with new SFC 100.
  • Consistent user data size in the process image.
  • CPU system identification possible via SZL 0x1C.
  • The cyclic self-test has been extended so that sporadic checksum errors are recognized and corrected before they take effect. 

The following errors have been corrected with Operating System V3.0:

  • In the case of S7-400 CPUs, the EXTF LED did not reset in certain circumstances after a failure of the battery backup. This has been corrected.
  • With S7-400 CPUs, a successful operating system update is now entered correctly in the diagnostics buffer.
  • In the 8x mode of the SFC39, only the "Substitute Event" w#16#5380 and no longer the OB start event is entered.
  • In certain cases, when operating flash memory cards in the CPU, it was necessary to perform a power off/on of the CPU after loading the STEP 7 project, because the CPU reported a parameterization error with startup fault. This has been corrected.
  • In the case of error event 6547 "Parameterization Error when assigning Parameters to K Bus Modules", the module number and slot of the DP master are specified in the detailed information of the event, because the master system ID cannot always be determined upon the error detection. It is likewise possible for inserted sub-modules to display the number of the interface module

Product information:  Product informationV30_H.pdf ( 58 KB )

Files for firmware version

 
 MLFB 
 V3.0.0 
 CPU 414-4HJ00 6ES7 414-4HJ00-0AB0  e4_4hj00.exe (939,8 KB)
 CPU 417-4HL01 6ES7 417-4HL01-0AB0  e7_4hl01.exe (940,5 KB)

 

 

 

 

 

 

 

Update V3.0.1 (Backup)

The following errors have been corrected with Operating System V3.0.1:

  • In an H system, central expansion units are attached to master and standby. If the voltage supply of the central expansion units breaks down at both the master and standby within approx. 4 ms, a synchronization error might occur after the voltage returns.
  • After numerous connection faults within short periods of time (e.g., several power off cycles), the CPU - in rare cases - entered the DEFECT mode.
  • A large number of monitoring tasks carried out simultaneously (same cycle) by an OS system could - in very rare cases - lead to a loss of synchronization loss in the H system. 
  • In V3.0.0, it was not possible to read out the time remaining of an activated (not yet started) time delay interrupt via SZL 0x222.
  • If a simplex I/O is assigned to rack 0 of an H system, DEFECT mode may occur in rack 1 when loading a configuration to the CPU.
  • The EXTF LED of the CPU remained lit and did not go out after a power off/on cycle or after the return of a DP standard slave (see FAQ 9824085).

Product Information Firmware V 3.0.1:   A5E73168.pdf ( 80 KB )   

Files for firmware version

 
 MLFB 
 V3.0.1 
 CPU 414-4HJ00 6ES7 414-4HJ00-0AB0  f4_4hj00.exe (950,9 KB)
 CPU 417-4HL01 6ES7 417-4HL01-0AB0  f7_4hl01.exe (952,2 KB)

 

Update V3.1.0 (Backup)

V3.1.0 contains the following Functional Enhancements:

  1. Configuration in RUN mode (stand-alone operation):
    Configuration in RUN mode (CiR) permits system expansions and rebuilding during the operating phase.
  2. Reparameterization of modules during the operating phase (within the framework of CiR).
  3. Avoidance of stops with the OB88 (processing stop):
    By programming the OB88, special programming errors will no longer cause a mandatory STOP (errors in the allocation of local data, nesting depth too high in the case of synchronous errors and block calls).
  4. Initiation of the topology determination with diagnostics repeater on PROFIBUS DP by means of SFC103.
  5. Operation of redundant I/Os.
  6. Connection of SIMATIC S5 expansion devices:
    Via an IM463-2 interface module, the connection of S5 I/Os for stand-alone operation of the CPU41x-4H is possible.
  7. DP master systems according to DPV1 and DP master systems according to EN 50170 can be employed in the same system. 

The following errors have been corrected in V3.1.0:

  • Under certain circumstances, a defect could occur in the CPU, whereby the diagnostics buffer would not contain a corresponding (defect) entry after a power off/on cycle.
  • When switching off the supply voltage to the last PROFIBUS DP station of a line (with bus terminating resistor), a loss of synchronization with the event ID 43DA could occur.
  • After repeated power off/on cycles, a PROFIBUS DP slave (according to EN 50170) would no longer be correctly accepted.
  • In an H system coupled with an APPLICOM PCI Ethernet module, the following defect could occur: 4550 / b003 / 8752 / 01ae.

Product information A5E00073168-08:  A5E73168_08.pdf ( 75 KB )   

Files for firmware version

 
 MLFB 
 V3.1.0 
 CPU 414-4HJ00 6ES7 414-4HJ00-0AB0   4144hj00_v310.exe (1018,3 KB)
 CPU 417-4HL01 6ES7 417-4HL01-0AB0   4174hl01_v310.exe (1019,2 KB)

 

 

 

Update V3.1.1 (Backup)

The following error has been corrected with Operating System V3.1.1:

  • In stand-alone mode of a H-CPU and also when using simplex I/Os in a H system, the following behavior could occur:
    In the case of frequent, in particular cyclic calls of the SFC 51 to read the SZL W#16#4C91 (module status information of a module at an external DP master interface module), it could happen that although the addressed module functions error-free, the error code W#16#8087 is permanently output on the SFC in the RET_VAL parameter. This condition could only be eliminated by an overall reset of the CPU.

Product information A5E00073168-09:  A5E73168_09.pdf ( 76 KB )

Files for firmware version

 MLFB 
 V3.1.1 
 CPU 414-4HJ00 6ES7 414-4HJ00-0AB0   4144hj00_v311.exe (1018,3 KB)
 CPU 417-4HL01 6ES7 417-4HL01-0AB0  4174hl01_v311.exe (1019,2 KB)

  

 

Update V3.1.3 (Backup)

The following errors have been corrected in V3.1.3:

  • When operating the diagnostics repeater with SFC103, the defect 4550 / B71D could occur.
  • If the communication load is high and several cyclic control & monitoring tasks have to be executed at the same time, a loss of synchronization could occur in very rare cases.

Product information A5E00073168-10:  A5E73168_10.pdf ( 80 KB )

Files for firmware version

 
 MLFB 
 V3.1.3 
 CPU 414-4HJ00 6ES7 414-4HJ00-0AB0  4144hj00_v313.exe (1019,2 KB)
 CPU 417-4HL01 6ES7 417-4HL01-0AB0  4174hl01_v313.exe (1020,2 KB)

 

 

Update V3.1.4 (Backup)

Corrections with Firmware V3.1.4:

  • The display of messages has been improved in the case of a cold restart of WinCC as well as in the case of application program changes.
  • If a large number of DP/DP couplers (IM157) was used in the H system, a synchronization error could occur in the case of a slave failure. This has been corrected.
  • Error correction in the H system for the case of a high communication load when using AG_SEND / AG_RECV

Product Information A5E00073168-11:  A5E00073168_11.pdf ( 73 KB )

Files for firmware version

 
 MLFB 
 V3.1.4 
 CPU 414-4HJ00 6ES7 414-4HJ00-0AB0  4144hj00_v314.exe (2,0 MB)
 CPU 417-4HL01 6ES7 417-4HL01-0AB0  4174hl01_v314.exe (2,0 MB)

 

 

 

Update V3.1.5 (recommended for upgrading)

Corrections with Firmware V3.1.5:

  • If a subsystem is powered off while in the redundant operating mode and a memory compression is active at the same time, the remaining subsystem might become inoperable in rare cases. 
  • With this version, it is possible to force bit memory addresses in ranges greater than 8191. 

Product Information A5E00073168-12:  A5E00073168_12.pdf ( 72 KB )

Files for firmware version

 
 MLFB 
 V3.1.5 
 CPU 414-4HJ00 6ES7 414-4HJ00-0AB0  4144hj00_v315.exe (2,0 MB)
 CPU 417-4HL01 6ES7 417-4HL01-0AB0  4174hl01_v315.exe (2,0 MB)