Dear

I would like to make two function blocks for an AEG Thyro-A controller. For this purpose, I want to create an FB for reading input words (for example PIW300 to PIW500) from the 8 AEG Thyro-A controllers and I want to create an FB to write the outputs for controlling the 8 AEG Thyro-A controller (for example PIW300 to PIW500). Is there a possibility to read these signals with one input parameter, for example by entering the start address PIW300 and entering the start address for the outputs QIW300 for the control, or is this not possible and must everything be linked manually, input word by input word? I hope someone can help me further. 

Thank you in advance,

Frederik

Hello,

really I don't understand to your question as principle, although I understand your requested idea. Question is how you want handle that area set, via some FOR cycle or what source system sets this expected address????? It looks to me like missunderstanding of functionality. It is simply easy to do some state machine and set multiple specific comm blocks with different destination address statically. look, best option is simply check your expected comm blocks you want use and its input parameters data type. I expect on other side that typical types as ANY or VARIANT in this case.

What you ask is possible.

This response of mine would already have been helpful if you bothered to mention which CPU is designed for with which design software. Mention also which program language you prefer - STL vs SCL, as LAD is out of the question.

without knowing anything about your specific requirements, some first examples

DPRD_DAT: Read consistent data of a DP standard slave

DPWR_DAT: Write consistent data of a DP standard slave

If a classic cpu is used, not the HW ID is used as LADDR, but the start IW/QW address.

regards

sancruz