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H-CPU handle Data from CP443-1

Created by: gino.chiu at: 1/20/2012 12:57 PM (4 Replies)

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1/20/2012 12:57 PM	Rate (0)
gino.chiu Posts: 3 Rating: (0)	Dear All Experts, I would like to ask about the mechanism of S7-400H Redundant PLC in handling data from CP443-1, such as TCP connection from 3rd parties devices. Here is the scenario: (See attachment shows the physical and logical connection) Normally, Processor A (3rd-party) communicate with CPU A via TCP protocol, and initially, both CPU A and B having a value of 0 in DB1.DBW0. A wire break occured, for example, it switches to communicate with CPU B. Then Processor A write a value of 1 to CPU B DB1.DBW0. I would like to know how 400H CPU respond to this, i.e. will Master CPU A write a 0 to CPU B as CPU A is Master. Or, CPU B will update the data to CPU A no matter which one is Master? I was asked by my client as they used to work on other PLC that Master CPU always overwrite data to Standby CPU. Just like the software redundancy for Siemens. I tried to find out more official document stating about this, but I couldn't find any. Would anyone pleasedescribe what will be the result, Result 1 or Result 2? Highly appreciated if you can advise any official document mentioned about this, so that I can explain to my client. Thanks very much!!!! Gino Attachment S7-400H & CP443-1.pdf (274 Downloads)
gino.chiu Posts: 3 Rating: (0)
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1/22/2012 4:10 PM	Rate (0)
poya_xp Posts: 167 Rating: (4)	Hi i think this can be helpful http://support.automation.siemens.com/WW/view/en/53385282 you can start from page 81 to what page that satisfy you.
poya_xp Posts: 167 Rating: (4)	Last edited by: O_Moderator at: 1/23/2012 9:20 AM llink corrected
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1/23/2012 5:36 PM	Rate (0)
smiffy Platinum Member Joined: 1/17/2007 Last visit: 10/21/2024 Posts: 1547 Rating: (537)	Well this is a very interesting question. I have had quite a lot of experience in this field, having designed a Modbus protocol interface block that works in a H-system. I don't think that the situation you have shown is possible. From what I managed to ascertain, the reserve CPU is not actually running the code, it simply "shadows" the master CPU. The instance and shared DB's are updated in the reserve CPU by the master CPU. So in your diagram, the reserve CPU will not be getting the data from the CP. Now given that each CP has a unique hardware address / Netpro ID you will different AG_XXXX calls depending on which CPU is currently master. I also made a discovery that the CPU in rack 0 can access the CP in the rack 1 via the sync link (and vice versa). So in you case, you would have 2 AG_XXXX calls, one using the rack 0 CP connection, and one using the rack 1 CP connection. The 2 calls would be selectively called depending on which CPU is master and which CP was being used for the connection. You could effectively treat the 2 CP's as main and standby connections. So if rack 0 (CPU A) is master, try getting data from CP in rack 0, if AG_XXXX call sucessful all well and good, the DB will be updated in CPU A and CPU B will be updated also via the sync link. Now if the AG_XXXX call fails for some reason (e.g. 8304 = connection dropped), the try getting data from CP in rack 1. Again if call suceeds that all is well. If this call fails also, you have a problem. So I suspect that you would just repeat the process again alternating between the 2 CP's till you get data from either CP. So if rack 1 (CPU B) is master, try getting data from CP in rack 1, if AG_XXXX call sucessful all well and good, the DB will be updated in CPU B and CPU A will be updated also via the sync link. Now if the AG_XXXX call fails for some reason (e.g. 8304 = connection dropped), the try getting data from CP in rack 0. Again if call suceeds that all is well. If this call fails also, you have a problem. So I suspect that you would just repeat the process again alternating between the 2 CP's till you get data from either CP. Hope that makes sense. I have done just this type of selective calling in my block and is works fine. I have some SCL code that shows you how I did it if you are interested.
	Programming today is the race between software engineers building bigger and better idiot proof programs, and the universe producing bigger and better idiots. So far, the universe is winning...
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This contribution was helpful to 2 thankful Users Jazz_M MicroMan

1/26/2012 5:16 PM	Rate (0)
gino.chiu Posts: 3 Rating: (0)	Dear poya_xp, Thanks for your help, but actually I've read this manual already. However, it seems that it doesn't mention deep enough on how both CPU execute the program and how the data flow between Master CPU and Reserve CPU after startup processing completed. I'm not clear about the role of Master and Reserve CPU on executing the program especially on communication function: i) Will both CPU will execute the user program, such as communication function, or only the master CPU does? ii) or only Master CPU will run the program and can make use of the CP module in Standby CPU Rack? And also on the synchronization of data, in the manual, it only mentions data will be synchronized: i) is it two ways of data flow? just like my diagram, will change of data in Standby CPU update to Master CPU? ii) Or Master CPU DB will always write to Standby CPU (similar to Software Redundancy). Thanks Gino
gino.chiu Posts: 3 Rating: (0)
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1/26/2012 5:27 PM	Rate (0)
gino.chiu Posts: 3 Rating: (0)	Dear smiffy, Thanks for your sharing. Have you try the Modbus TCP function block provided by Siemens? I've read that manual "Open Modbus / TCP Redundant Communication via CP443-1 in H-Systems" And I found that both CPU A and CPU B will have the same DB for the register table. And for 4 logical connections like the diagram I've attached in previous post, both 4 connections can be activated and listern to the communication partner. if there is only one DB for the register table. Then I'm not sure how the H-System will handle the function, is it as you've mentioned, Master CPU will execute the logic and use also the CP module on another rack, or both CPU execute the function? Did you find any document mention about this (master CPU execute logic and can access to the CP on another rack)? Thanks. Gino
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