Industry Online Support
Technical Forum
Navigation
architecture where bus redundency is established with not-redundent CPU
Created by: SOMA C. at: 10/2/2024 2:52 PM (0 Replies)
Rating 
Thanks 0
1 Entries
| 10/2/2024 2:52 PM | |
Joined: 1/25/2022 Last visit: 10/2/2024 Posts: 1 Rating:
|
Is it possible to make a architecture where bus redundency will be established with not-redundent CPU. In this architecture two CPU will communicate with individual RIO but in case of failure of any one CPU another CPU can take care of both the RIO. Please guide whether it will work or not ? ------------------------------------------------------------------------------------------ |
Last edited by: Moderator_Lan at: 10/02/2024 15:07:45Text formatting optimized Last edited by: Moderator_Lan at: 10/02/2024 15:14:14New subject after splitting |
|
Follow us on