HSC Encoder Zeroing with Sync input using LAD logic

qwazee

 Hello.

ibrahim454

Thanks for code, 
can you clarify these two value ;

The current encoder count is captured {#dintEncBias}, when captured? captured by Z pulse ?
and position {#realDegBias}: is this reference point?

Earlier was stated:

qwazee

<snip>
You do not need the Z-axis for the following concept.
You should not allow the HSC to be zeroed by any outside signal.
The count of the HSC is left as is.
</snip>

 

qwazee

<snip>

1. On startup you mark a bit that blocks movement until the user manually moved the rotary axis in position.
   
   
2. The user moves the system to a position. It is best if it is a fixed position. This could be two markings, one at a fixed position and one on the rotary part.
   
   
3. The user confirms that the manual correction is done. Continue to the next step if the position is fixed. Else the user should say which position is used as a reference.
   
   
4. The current encoder count is captured {#dintEncBias}, as well as the position {#realDegBias}. The position could be fixed or user defined. This is the reference point for all future positions. It is legal for as long as the PLC is powered or until the user reference the position again.

</snip>

In other words (operational procedure):
a) Power on

b) User activate manual mode

c) User jogs movement to a position

d) User tells the machine the degree position
     Position is saved  ........................... realDegBias

e) PLC program reads the position of the encoder
      Position is saved........................... dintEncBias

f) The two saved positions are used for as long as the PLC is powered

g) The HSC is never zeroed by the PLC program

Good luck

Hello, Newbie here, I've read all your investigations and observed the knowledge as I could.

Please forgive my lack of experience... is there any way for this job to be done using LAD logic? Will there be any delay in CPU processing with LAD logic??? Soon I must do a job similar to this one using a 1215C DC/DC/DC CPU with firmware 4.4

I'd be grateful for any pro tips!

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Split from HSC Encoder Zeroing with Sync input.

Sami4789

Hello, Newbie here, I've read all your investigations and observed the knowledge as I could.

Please forgive my lack of experience... is there any way for this job to be done using LAD logic? Will there be any delay in CPU processing with LAD logic??? Soon I must do a job similar to this one using a 1215C DC/DC/DC CPU with firmware 4.4

I'd be grateful for any pro tips!

1) Yes it can be done in LAD. Use the CALCULATE block.

2) Processing LAD may be a little slower if you use multiple temp tags and many blocks. But it is not enough to be concerned about it.

You can insert SCL networks between the LAD code. Right click on a network title to see the option. This would deliver compact written code inside LAD code. Seriously consider this.