7/26/2023 3:12 PM | |
Joined: 7/19/2022 Last visit: 8/12/2024 Posts: 380 Rating: (62) |
Hello U_362d85c0-5b14-4..., I have been testing it and in principle I have made the following clear (referring to your example):
Therefore, the only difference that I see is that in the NEG block, in addition to activating the output with the falling edge, it also activates when the M_BIT variable is at 1. |
If this Information really helps, you could use the Rate function |
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8/7/2023 3:46 AM | |
Joined: 10/7/2005 Last visit: 8/9/2024 Posts: 3016 Rating: (1054) |
In simple terms (see also attached inbuilt help comparison):
While technically correct for TIA Portal, this is classic STEP7 where NEG is for negative edge detection of a bit and NEG_I or NEG_DI are used for Two's complement |
Cheers |
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8/8/2023 7:10 AM | |
Joined: 10/7/2005 Last visit: 8/9/2024 Posts: 3016 Rating: (1054) |
You can use either to suit your needs but it depends on what your needs are. Anyhow, attached example pic and logic hopefully helps and can in either case be used for your own testing with a PLC or PLCSIM. |
Cheers |
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