Hello there, I am a new user of PCS7 and i have a simple question. I have inserted the blocks in the picture and in test mode, it seems like the inputs have no influence on the outputs of the blocks. I need to know if what i am doing is possible or is there another way to do that.

Thank you for your help :)

Hello Mohamed, 

After modifications to the CFC charts (connection addition, deletion etc.) , it is expected to compile and download the charts before enabling test mode. 

If at all the compilation and download of the charts is not done and the user clicks on Test mode activate button, the user will see a pop up stating, "Program change since the last compilation. Please compile chart and download to CPU. Register CPU for debugging?"

If the user clicks on 'Yes' here, the test mode will still be enabled but it won't work (get updated) for the changes done. 

I have attached a screenshot of my logic which is not compiled and downloaded before enabling the test mode. You will be able to see that the test mode depicts a wrong output for the updated block with new input connection. 

Hope this helps! 

I faced such problem two times in two differnt systems. One has pcs7 v6.0 sp2 hf1 and the other pcs7 v8.0sp2.

There had not been any change in program an every thing had been working fine in system since the problem was occured.

The problem was that the output of digital channel drivers didn't have any reaction to real hardware DI state.

There were no alarm in SM,IM,CPU and channel driver( 80 quality code,qbad=0)

The problem was solved by general reset and redownloading the projects to H_ systems(s7-400h).

But never find how they come.( may be updating firmwares lead to avoid these cases in future?)

Regards

Hosein