We had a problem at work. I have made similar but simplified version of it. A bit (M10.2 here) after getting set is being reset by an on-delay timer (T3 here). But when the timer time is finished, the timer should become high and set the subsequent bit (M10.4) in the following network as logic flows from top to bottom. But here bit 10.4 will never become high as timer becomes LOW from the first network. I want to know why this happens. If there was some logic with memory bit / data block memory it would have set that bit. Is the timer evaluation happens after one scan of OB1?

M10.4

--(S)--

Put that on the same network as the timer, so the timer will set the merker when the ET has elapsed.

Hati

M10.4

--(S)--

Put that on the same network as the timer, so the timer will set the merker when the ET has elapsed.

 No. That's not working either. That's why I want to know the sequence when timer is evaluated. Otherwise I can solve the problem by writing set and reset in different network using --(S)-- and --(R)--. 

Anvesh Jadav

 

Hati

M10.4

--(S)--

Put that on the same network as the timer, so the timer will set the merker when the ET has elapsed.

 No. That's not working either. That's why I want to know the sequence when timer is evaluated. Otherwise I can solve the problem by writing set and reset in different network using --(S)-- and --(R)--. 

 Move the SET BIT network after the timer.

Regarding timer evaluation, that you can read from the insoftware help.