Hi,

One of our customer's S7400H system faulted today with both CPU stop indication flashing. We had to hard reset and download complete program to restore the system to normal. Any advice for a solution or reason please share

attached log file from CPU

San

Here is info on Flashing LED

Section 5.6 Operating sequence for memory reset from “System Manual, 12/2010, A5E00267695-07 ” and,

Section 5.4.2 Performing a memory reset from System Manual, 07/2014, A5E00267695-13.

Operating sequence for memory reset
Case A: You want to download a new user program to the CPU.
1. Set the switch to the STOP position.
Result: The STOP LED is lit.
2. Toggle the switch to MRES, and hold it in that position. In this position the mode selector
acts as pushbutton.
Result: The STOP LED is off for one second, then on for one second, then again off for
one second, and then it remains lit.
3. Then release the switch, return it to MRES within the next 3 seconds, and then release it
again.
Result: The STOP LED flashes for at least 3 seconds at 2 Hz (memory is reset) and then
remains lit.

Case B: The STOP LED is flashing slowly at 0.5 Hz. This indicates that the CPU is
requesting a memory reset (memory reset requested by system, e.g. after a memory card
has been removed or inserted).
Toggle the switch to MRES, and then release it again.
Result: The STOP LED flashes for at least 3 seconds at 2 Hz, the memory reset is executed,
and the LED then remains lit.

@ San,

1. Please clarify what you mean by normal in your statement, “We had to hard reset and download complete program to restore the system to normal.” Did the CPU's return to normal operation after and this Diagnostic Buffer info is from before the “hard reset”

    

2. The 7 events from the uploaded Buffer file below, with Bold text to take note of.

Comments:         Both Rack0 and Rack1 Diag Buffer flles required, pls upload. See info after all events listed below for further details.

Diagnostic buffer of module CPU 414-4 H

Order No./ Description                 Component                       Version                       
6ES7 414-4HM14-0AB0               Hardware                          1                             
- - -                                                   Firmware                          V 4.5.5                       
Boot Loader                                   Firmware expansion        V 4.5.0                      

Rack:                             ---
Slot:                             ---

Serial number: SVPC3690064

Event 1 of 7:  Event ID 16# 49A4
STOP: inconsistency in the configuration data                                                 Inconsistency issues in the configuration data
occurred when checking Parameters for internal consistency
No consistency entries assignable
Error type: Time stamps of the loaded parameter fields do not match
Previous operating mode: STOP (internal)
Requested operating mode: STOP (internal)
Event occurred in the master CPU in rack 0                                                      Master CPU in rack 0
External error, Incoming event
12:00:38.439 AM  01/01/1994
(Coding: 16# 49A4  F844  C17B  0004  0000  0131)

Event 2 of 7:  Event ID 16# 530D
New startup information in STOP mode
Startup prevented by:
Loading user program or internal inconsistency detected                              Inconsistency issues
(SDBs less than 200 incomplete, superfluous, or incorrect)
- Cold restart or warm restart necessary
Startup information: 
- Time for time stamp at the last non backed up power on
- Single processor operation
Current/last startup type:
- No startup type/following memory reset
Permissibility of certain startup types: 
- Manual warm restart permitted
Last valid operation or setting of automatic startup type at power on:
- No startup type/following memory reset
Operating mode: STOP (internal)
Event occurred in the master CPU in rack 0                                                 Master CPU in rack 0
Incoming event
12:00:38.439 AM  01/01/1994
(Coding: 16# 530D  F804  C777  0140  0000  0700)

Event 3 of 7:  Event ID 16# 530D
New startup information in STOP mode
Startup prevented by:
Loading user program or internal inconsistency detected                         Inconsistency issues 
(SDBs less than 200 incomplete, superfluous, or incorrect)
- STOP request exists
- Keyswitch set to STOP
- Cold restart or warm restart necessary
Startup information: 
- Time for time stamp at the last non backed up power on
- Single processor operation
Current/last startup type:
- No startup type/following memory reset
Permissibility of certain startup types: 
- Manual warm restart permitted
Last valid operation or setting of automatic startup type at power on:
- No startup type/following memory reset
Operating mode: STOP (internal)
Event occurred in the master CPU in rack 0                                                Master CPU in rack 0
Incoming event
12:00:38.439 AM  01/01/1994
(Coding: 16# 530D  F804  C777  0161  0000  0700)

Event 4 of 7:  Event ID 16# 530D
New startup information in STOP mode
Startup prevented by:
- STOP request exists
- Keyswitch set to STOP                                                                                  CPU in Rack 0 Key Switch set to Stop preventing Startup
- Cold restart or warm restart necessary
Startup information: 
- Time for time stamp at the last non backed up power on
- Single processor operation
Current/last startup type:
- No startup type/following memory reset
Permissibility of certain startup types: 
- Manual warm restart permitted
Last valid operation or setting of automatic startup type at power on:
- No startup type/following memory reset
Operating mode: STOP (internal)
Event occurred in the master CPU in rack 0                                             Master CPU in rack 0
Incoming event
12:00:30.611 AM  01/01/1994
(Coding: 16# 530D  F804  C777  0061  0000  0700)

Event 5 of 7:  Event ID 16# 43F1
Switchover of master CPU and standby CPU                                           Master CPU in Rack 1 switches to standby and Standby CPU in Rack 0 switches to Master
Previous operating mode: STOP (own initialization)
Requested operating mode: STOP (own initialization)
Event occurred in the master CPU in rack 0                                            Standby CPU in Rack0 switched over to Master 
Incoming event
12:00:28.807 AM  01/01/1994
(Coding: 16# 43F1  F833  0000  0000  0000  0000)

Event 6 of 7:  Event ID 16# 430E
Memory reset executed                                                                              Memory Card Reset executed    
Initialization information: Memory reset due to inconsistent data
Previous operating mode: STOP (memory reset)
Requested operating mode: STOP (own initialization)
Event occurred in the standby CPU in rack 0                                         Standby CPU in Rack0
Incoming event
12:00:24.071 AM  01/01/1994
(Coding: 16# 430E  F023  CE00  0000  0000  0008)

Event 7 of 7:  Event ID 16# 4309
Memory reset started automatically (power on not backed up )            This might be an indication of an issue with the memory card.
Initialization information: Memory reset due to inconsistent data
No relevance for user (Z1): 0001
Previous operating mode: No voltage
Requested operating mode: STOP (memory reset)
Event occurred in the standby CPU in rack 0                                          Standby CPU in Rack0
Incoming event
12:00:24.055 AM  01/01/1994
(Coding: 16# 4309  F0F2  CE50  0001  0000  0008)

Section 9.3
Link-up and update sequence

There are two types of link-up and update operation:
● Within a "normal" link-up and update operation, the fault-tolerant system should change
over from single mode to redundant mode. The two CPUs then process the same
program synchronized with each other.
● When the CPUs link up and update with master/reserve changeover, the second CPU
with modified components can assume control over the process. Either the hardware
configuration, or the memory configuration, or the operating system may have been
modified.
In order to return to redundant system mode, a "normal" link-up and update operation
must be performed subsequently.

How to start the link-up and update operation?

Initial situation: Single mode, i.e. only one of the CPUs of a fault-tolerant system connected
via fiber-optic cables is in RUN.
To establish system redundancy, initiate the link-up and update operation as follows:

● Toggle the mode selector switch of the reserve CPU from STOP to RUN.
● POWER ON the reserve (mode selector in RUN position) if prior to POWER OFF the
CPU was not in STOP mode.

● Operator input on the PG/ES.

A link-up and update operation with master/reserve changeover is always started on the
PG/ES.
NOTICE
If a link-up and update operation is interrupted on the reserve CPU (for example due to
POWER OFF, STOP), this may cause data inconsistency and lead to a memory reset
request on this CPU.
The link-up and update functions are possible again after a memory reset on the reserve.

Section 7.2

Consistent data

Data that belongs together in terms of its content and describe a process state at a specific
point in time is known as consistent data. In order to maintain data consistency, do not
modify or update the data during their transfer.

Example 1:
In order to provide a consistent image of the process signals to the CPU for the duration of
cyclic program processing, the process signals are written to the process input image prior to
program execution, or the processing results are written to the process output image after
program execution. Subsequently, during program processing when the inputs (I) and
outputs (O) operand areas are addressed, the user program addresses the internal memory
area of the CPU on which the process image is located instead of directly accessing the
signal modules.
 

Example 2:
Inconsistency may develop when a communication block, such as SFB 14 "GET" or SFB 15
"PUT", is interrupted by a process alarm OB of higher priority. If the user program modifies
any data of this process alarm OB which in part have already been processed by the
communication block, certain parts of the transferred data will have retained their original
status which was valid prior to process alarm processing, while others represent data from
after process alarm processing.
This results in inconsistent data, i.e. data which are no longer associated.