11/8/2018 1:19 PM | |
Joined: 3/14/2008 Last visit: 9/26/2024 Posts: 2098 Rating: (938)
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Hi Ziemens, A better way I think is to include a SCL block between the inputs and interlock. 8 inputs for the interlock and 8 outputs directly connected to interlock (only passthrough). In SCL you can make a simple logic,where you check which signals is triggered first..Output INT: FirstSignal shows which signal is triggered. Something like:
PS: The APL interlock Intlock2 etc. already features a first signal detection
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Last edited by: Oreca at: 11/8/2018 1:19:46 PMIf I could help you, you can use the RATE button. Thank you. |
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