Hello,

we don't see what you did in your S7-1500 prg but in case of use comm modules, some comm blocks need to be prepared in your code, probably on both sides. What blocks maybe depends what kind of data you want from Slave. I recommend check your CP S7-1500 module Help (System Manual), there must be info what kind of comm blocks you need use for what type of data. Generally, in case of consistent data I expect DPRD_DAT and DPWR_DAT blocks but check Manual for sure. Other good help is TIA (your version) System manual wher is also this problematic described. Don't hesitate ask next questions, maybe attach some zip file with screenshots from your cfg and code parts.

Update: here is link to good PDF, check for possibilities due Protocols and Master HW:

Simatic CPU to CPU communication

Hello,

yes, as I was mentioned before (expected).