Hi guys,

I'm new in SCL programming, so please have patience:)

I want to compare the bits from an array with zero. The array is created with 16 BOOL variables and all I want to do is when some of these 16 BOOL variables is not equal to zero to set another variable to 1, I mean I'm using this as a precondition.

I have this created in STL, but I'm having problems with the SCL because I don't know the sintax yet.

This is the code in STL:

LAR1  P##stopconditions // local array variable with 16 BOOLs
L W [ AR1 , P#0.0 ]
T     DB100.DBW102
L     16#0000             
<>I
=     #Stopconditions_active // Local var as a result

Can someone tell me if there is some kind of manual or some basic instruction list where I can see the how to compare two variables, how to set/reset var etc. I have seen a lot of Siemens official manuals about SCL but there I can't understand anything, I mean I can't find what I'm looking for.

Thanks in advance

Hi,

I just checked the LAR1 instruction -> this can only used in STL. Please check page 29 in  the following link.

SIMATIC S7-1200 / S7-1500 Comparison list for programming languages based on the international mnemonics

I can also give you a Getting Started for SCL - please check this:

https://support.industry.siemens.com/cs/de/de/view/18735131

Regards,

Towome

Hi Smiffy,

I didn't understand this: iBitArr AT BitArr : INT; // Overlayed INT at the same address as BOOL array 

What is AT? And how can I overlay the address to the one of the array variable?

I'm using Siemens S7 300 PLC with Tia portal.

In the FC under Temp I'm defining:

BitArr: array [1..15] of bool (with offset address 2.0)

Thx

Hi drozerce,

Ur task can be solved even without comparing array bits. But see how it can be done.

Define i as integer and use FOR loop

FOR i = 0  to 15 By 1 Do

If BitArr[i] = 1 Then #Stopconditions_active := 1; Endif; End_for;

SOMEWHAT OFF TOPIC

smiffy

Oh, I have just seen that you are using TIA. In TIA the blocks have the property "optimized data access" set by default. When this property is set, the AT operator is outlawed. So you have 2 options: Either turn off optimization for the block, or use an alternative method as shown in the previous post.

Not sure - drozerce was probably talking of Step7 Classic.

smiffy - you do not have to deselect the code block from optimized.
There is a method I discovered that is now also written in an FAQ.
You set the one setting to "Set in IDB" - - notice the NOTE in LINK.

This can work for the one issue you had a problem with too.

@drozerce: Overlay is where more than one tag is sharing the same memory bit space. Have a look at [LINK] and the links provided. Do notice that these are written for S7-1x00 PLCs.

 Even more OFF TOPIC

smiffy

IF iBitArr <> 0 THEN
    ArrAnyBitSet := 1;
ELSE
    ArrAnyBitSet := 0;
END_IF;

Or simply: 

ArrAnyBitSet:=iBitArr<>0;

Hi all, and thanks for the tips...

But, as I have mentioned in my topic at the beginning I'm working on CPU 315, so with that reason I believe that I can't use the overlaying thing, unfortunately.

#Sachinpatke: I believed that your tip suits me the most, but when I created it seams that it is not working properly. Actually, #stopconditions are always 0, because I assume that it is overcopied by tho others bits. For example, if I write like this:

For i:=1 to 16 by 1 do

if #stopconditions[I]=1 then

#stopactive:=1;

else

#stopactive:=0; 

Then i is all the time changing from 1 to 16. If i:= 1, and #stopcondition[1]:=1 than #stopactive is 1, but in the same time (or the very next cycle time) i:=2, and #stopcondition[2]:=0 and #stopactive:=0 and actually I get for #stopactive:=0 all the time. That's why I think this solution is not suitable for my case.

Other tips as I saw are related to "AT overlay", so for now I can't use them, but they are good for the future.

drozerce

But, as I have mentioned in my topic at the beginning I'm working on CPU 315, so with that reason I believe that I can't use the overlaying thing, unfortunately. 

The SCL for S7-300/400 supports AT overlay. Manual. Chapter: 8.4.