7/30/2009 10:41 PM | |
Posts: 7 Rating:
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Does the SRD instruction work for a 32 bit move. We have code where we move a double word by 32 bits to check the status of the MSB via a JP instruction as the last bit shifted out goes to CC1. If it is a 1, then we go out of a loop. We are having the issue of the CPU (we are using a CPU319) go into stop mode on "cycle time exceeded" fault. We figure this is because for a 32 bit move, the SRD instruction for some reason does not set the CC1 high even though the MSB for the double word was 1, which traps us in an infinite loop causing the CPU to go to stop mode on cycle time exceeded. Either this, or something may be happening to CC0, as for the JP instruction will only take us out of the loop if CC1=1 and CC0=0. Maybe for a 32 bit move, CC0 is not being reset to 0. The code we use is attached. We have used this code to scroll through Low level messages to be displayed on an HMI. The issue only occurs of only Low level message 32 or 64 is to be displayed. The CPU does not go into stop mode if multiple bits of the LL messages double word are high, and only goes into stop mode when the only LL message to be displayed is Message #32 or 64. Also, even if other LL message bits are high, and the CPU does not stop because of Message #32/64 bit going high, message#32/64 are not displayed. Code is attached for ready reference. Attachment64_Message_Scroll.zip (349 Downloads) |
8/1/2009 12:26 PM | |
Joined: 10/7/2005 Last visit: 4/24/2025 Posts: 3047 Rating:
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no need to correct you Tauseef, as your assertions are correct.
I did(quickly) test your FC501 with PLCSIM and wasNOT able to reproduce the problem that you described (i.e. IMHO your FC works the way you intended it to work). In light of this I wonder if you have an "undocumented feature" in your 319 firmware (which does seem to have had more than its fair share ofbugfixes with every FW release). I suggest toupdate your 319 to thelatestfirmware and test your logic again (and/or try it in PLCSIM first for yourself should you have PLCSIM). Here are the links for the firmware (V 2.81 is the latest at time of posting this): 319-3 PN/DP 319F-3 PN/DP I hope this helps |
Cheers |
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8/4/2009 7:43 PM | |
Posts: 7 Rating:
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Sydney, AttachmentLL_Message_scroll.zip (336 Downloads) |
8/5/2009 3:45 AM | |
Joined: 10/7/2005 Last visit: 4/24/2025 Posts: 3047 Rating:
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I need to disagree with Sydney on this one(sorry Sydney) and stick with my original assertion (it is a firmware issue). Having the unconditional jump will certainly not "hurt" and (apart from making the code "clearer") avoid that you unnecessarily execute the 6 instructions of the second part of the Network, but that is all it will achieve (i.e. IMHO it is NOT the cause of your problem). Executing an SRD with a "negative" value or a value bigger than 32 in accu2-L-L will simply lead to a reset of CC1 and CC0, which means the(unnecessarily executed) second part of the Network willonly "cost" you the extra execution times of6 lines of logic (perbitsearch for the first 32 bits). Bottom line is Tauseef that you are using the SRD and JP instruction correctly and my money is (as before) on a firmware issue with your 319. Attached is a screendump which showsa few SRD examples and the CC1&0 results the way you would expect them (tested with PLCSIM V5.4 SP3). I hope this helps |
Last edited by: fritz at: 8/5/2009 4:15 AMUploaded missing attachment Last edited by: fritz at: 8/5/2009 4:13 AMCorrected typos Cheers |
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