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M memory bit shows two different states in VAT
Created by: j.kowalski at: 5/22/2021 5:00 PM (1 Replies)
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2 Entries
| 5/22/2021 5:00 PM | |
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Posts: 32 Rating:
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Hello, I have an issue where M memory bit shows two differen states in VAT and in FB, just to confirm that I checked where is it written from just in case is written more than 1 time in 1 cycle. In vat shows true but definitelly not as this is required to run conveyor but it is not running. Any help would be much appreciated ------------------------------------------------------------------------------------------ |
Last edited by: Jen_Moderator at: 05/25/2021 06:12:42New subject after splitting |
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| 5/25/2021 6:19 AM | |
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Posts: 8171 Rating:
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Closed cause question posted twice. The second thread with the subject Two different states of M memorty bit while monitoring. is published within the conference STEP 7 / STEP 7 Lite. Best regards, |
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