Analyzing PLC cycle time

Hello to all,

How can I analyze PLC program in TIA project loaded to PLCSIMAdv. in order to determine which part of the program contribute the most to the high cycle time?

The question is general, and I'm interested to learn how to approach this problem , what are the steps in analysis and  optimization of the cycle time.

How much do you need to lower your PLC scan time?

Now for the real questions that relate to the project given the time investment required to find and then optimize everything you might want to optimize (for any project):

• Is this for a one-off project never to be repeated?
• Is this for a prototype for 10+ future clones based on the results of this project?
• How much is your time worth?

If you have time, download and integrate the Siemens profiling library components into a copy of your project.  Once the various OBs/FBs/FCs are analyzed during the various process situations, you can determine which blocks can use further scrutiny.  If you have a single network in an OB and need to know how long it takes, put it in an FC (cut/paste from OB to FC), and let the profiler analyze the FC.

https://support.industry.siemens.com/cs/document/109750245

That link is a good starting point.

If you want to do it yourself, you can use the RUNTIME instruction.

Remember each question asked above when making decisions on what route you need / want to take.

If you simply want a challenge and money is no object and you have as long as it takes, you can go with the firmware profiling option.

And then reality steps in and the other questions may help you make a more realistic approach for your specific needs.

Lastly, if it is a one-off project and PLC scan time is too slow, increase the S7-1500 level 1-2 notches.  If you are using s7-1512, increase to 1513 or 1515.  If a 1513 is too slow, bump up to 1515/1516.  Likewise if a 1515/1516 is too slow, jump all the way up to 1518.

Remember, premature optimization is usuallly a waste of effort when usually the logic is going to run fast enough to do the job with even average competence at PLC logic programming, data structure choices (UDTs / DB structs / etc), and the ability to avoid LOOPS in PLC logic except for very short deterministic loops (like i = 1 to 10, not like i = 1 to n).

Build in enough space in the S7-1500 mounting bracket for 3 sizes higher s7-1500, and simply build it and let it rip.  If you need a higher level PLC to drop scan time, that's much less expensive and faster than going through and pre-optimizing logic that has never run.

Most of the PLC's time is wasted waiting for events (digital signals, comm signals) to happen so it can do something else and wait.

Jasner

Hello to all,

How can I analyze PLC program in TIA project loaded to PLCSIMAdv. in order to determine which part of the program contribute the most to the high cycle time?

The question is general, and I'm interested to learn how to approach this problem , what are the steps in analysis and  optimization of the cycle time.

Actually, I noticed that cycle times longer on PLCSimAdv comparing to real hw PLC. Also, I had a lot of dynamization (monitoring) windows open.

That is why I asked this rather general question, what should I do if the cycle time becomes too big and how to analyze and optimize that.