11/28/2010 12:55 PM | |
Joined: 10/7/2005 Last visit: 9/23/2024 Posts: 3022 Rating: (1054)
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Hello saddlepoint I wonder if you are doing the cycle precise aquisition or not. If you are, you should probably ask autem for a reason as M0.0 will be ON as soon the rising edge detection takes place (which is the same scan when I 0.0 goes from 0 to 1). If you aren't, then you shouldn't be suprised that their status is not "synchronised" when aquired (theyare in two different memory areas of the CPU, one in the Process Image the other in the M area which in non cycle precise aquisition may be handled with two seperate read request by autem's analyser, again perhaps worthwhile checking with autem). I hope this helps |
Cheers |
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11/29/2010 12:55 AM | |
Joined: 10/7/2005 Last visit: 9/23/2024 Posts: 3022 Rating: (1054)
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There is no delay dear hdhosseini (unless you mean the apart theexecution time of the --(P)--instruction) andI wonder ifyou misread/misunderstood the description and diagram in the Hans Berger book. The rising edge detection memory bit (the addressabovethe --(P)-- instruction in LAD / behind the FP instruction in STL) will be set to 1 there and then at the moment in time when a rising edge of the checked signal takes place.
It is compulsary because the PLC uses thisbit to compare the RLO before the--(P)--instruction with the statusof the memory bitto be able to detect therising edge. In the old S5 daysthere was no --(P)--(or --(N)--) instruction and rising edge detection was commonly done asshown below (example for the addresses that saddlepointused): [code]A I 0.0 AN M 0.0 S M 0.0 // rising edge memory bit = M 0.1 // one shot bit AN I 0.0 R M 0.0 [/code] All that the --(P)--(or --(N)--) instruction dois to simplify the logic, the principle behind it remains the same though. My advise to you stays as before, just one more thing to bemindful of: If you aren't doing cycle precise aquisition, you'll also need to bear in mind thatI0.0 will be oneat the start of thecycle (updated as part of the process image), M0.0 will however only be 1 once the --(P)--instructionrelated part of the program is executed(this is however still in thesamecycle, so a cycle precise aquisition at the end of the cycle mustshow I 0.0 and M0.0 coming ON together). |
Cheers |
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11/30/2010 1:18 AM | |
Joined: 1/28/2009 Last visit: 9/10/2024 Posts: 6849 Rating: (1365) |
Dear Saddlepoint Please check the attachment which compares 2 signal diagrams for rising edge detection. The diagram in right side extracted from online help of STEP7, note that input signal and edge memory are identical. The diagram in the left side reveals the microcontroller inside PLC needs time to detect change by comparing RLO before FP and edge memory. Microcontroller sets edge memory to (1) if RLO before FP (1) and edge memory (0). For a better understanding read chapter 7 of Infineon's C166 Family Instruction Set Manual and Table11 Minimum Instruction State Times. [quote ] We discuss procedure of how FP and FN processed, we remember this exactly for one or two weeks but after that gradually we forget details. This is the fact I tried to convey ironically, in long term we just remember general concepts or topics. This why we need references to check while needed. regards AttachmentFP.zip (163 Downloads) |
Last edited by: hdhosseini at: 11/30/2010 1:43 AM |
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11/30/2010 5:26 PM | |
Posts: 19 Rating: (0) |
Thank you all, I got the point. saddlepoint |
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