4/19/2012 11:34 AM | |
Joined: 1/28/2009 Last visit: 9/10/2024 Posts: 6849 Rating: (1365)
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Hello Thura, One of the question which can be solve easily. Now slution provided by 1-simple "FB41" which is a PID function block 2-FB67 as the rate limiting function which is developed by me 3-FB68 as first order filter for process simulation.it is developed by me by Euler method [code] L #OB35_EXC_FREQ ITD T "reg".sample T "proz".INTERVAL CALL FB 1 , "reg" enable := pv_analog := zeit :=T1 set := sample := ana_out := out_real := time_passed:= L "reg".out_real T "hd".input CALL FB 67 , "hd" input := rst := step := factor:=1.000000e+000 high :=1.000000e+002 low :=0.000000e+000 out := first := // CALL FB 68 , "proz" F :="hd".out A :=4.000000e+000 B :=1.000000e+000 INTERVAL:= Y := REST := L "proz".Y L 1.000000e+002 /R L 2.764800e+004 *R RND T "reg".pv_analog[/code] Also check the archived project uploaded. Best regards, Hamid Hosseini AttachmentQtest2.zip (275 Downloads) |
Last edited by: hdhosseini at: 4/19/2012 11:45 AM//Archived Project updated |
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4/19/2012 1:23 PM | |
Joined: 1/28/2009 Last visit: 9/10/2024 Posts: 6849 Rating: (1365)
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And this is the video file to show the process of testing whole control set up via a variable table. Best regards, Hamid Hosseini Attachment4-19-2012 3-18-38 PM.zip (266 Downloads) |
This contribution was helpful to1 thankful Users |
5/7/2012 9:28 AM | |
Joined: 1/28/2009 Last visit: 9/10/2024 Posts: 6849 Rating: (1365)
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Hello Marko Bursic, We seek new suggestions,if possible actualize(realize) your idea in our conventional language based on problem here Layout.JPG .I mean we need a project to test the idea.Hopefully,results would be awesome. Best regards, Hamid Hosseini |
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