3/18/2009 12:29 PM | |
Posts: 2348 Rating: (264) |
I can recommend using http://support.automation.siemens.com/WW/view/en/20443243 and Step7 integrated help with topic "ANY data type" To be short: ANY is pointer type which points to area (not particular variable, but range of variables). For exampleP#DB1.DBB20 REAL 5 (range of 5 reals beginning atDB1.DBB20). P area - didn't met anywhere, usually I or Q is used. V area - it's local stack area of calling block. You see, parameters with length > 4 bytes can't be trasfered to called function. In this case pointer to such parameter is written to local data of calling block and only pointer trasfered. So in called block this data is accessed via P#V... As for parameter types = also never met. In theory such project structure can exist, but in practice i didn't find any advantages it could give. If someone has more info - please share:^) |
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3/18/2009 2:54 PM | |
Posts: 557 Rating: (64) |
HI Thanks for your reply. i think these all are the machine code, siemens has givenhelp in ANY data type in simatic manager softwere. but there is no example for these code.my understanding is plc is digital operating electronic sytem, it can understand 0(low) or 1(high) for exampledigital input signal==80 in hexa(bin 10000000) it mean I0.0have some machine code. siemens has given all code,but there is no example if anybody know please put by example. regards |
3/18/2009 6:36 PM | ||||||||||||||||||||
Posts: 2661 Rating: (279) |
Hi Eastern, P is for periphery area (without process image). For example IW20 in the process image corresponds to PIW20 in the periphery. The first table in your postrepresents area codingin theANY & DBpointers and the second table represents the data type coding in the ANY pointers. These codes are not machine codes... They are very useful for preparing ANY pointers using indirect addressing inside an FBwith temp data. The structure of the ANY pointer for data types is as follows:
Regards Added: I have made an example (STL source attached) for transferring 10 input bytes to 10 output bytes in an FB using SFC20:BLKMOV. AttachmentBLKMOV_EXAMPLE.zip (434 Downloads) |
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Last edited by: Phantom75 at: 3/18/2009 8:43 PMAttached Example |
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3/19/2009 5:32 AM | |
Posts: 557 Rating: (64) |
hi Thanks for your reply. please find the attachment for some code program.if anybody have more idea please share. regards AttachmentCODE.zip (451 Downloads) |
3/19/2009 9:41 AM | |
Posts: 2348 Rating: (264) |
Hmm, when i was trying P area in pointer few years ago i didn't succeed. Maybe i did something wrong (i was learning that time), but i couldn't get PIW.. Will check that:^) What about mashine codes - it may be true, but with similar probability it may be wrong^) |
3/20/2009 5:18 AM | |
Posts: 557 Rating: (64) |
HI Aret, I got some program for p area....... try this L DW#16#80000001 LAR1 // P0.1 A M[AR1,P#0.0] // A M0.1 REGARDS |
3/20/2009 6:23 AM | |
Posts: 2348 Rating: (264) |
Thanks, Eastern. But it's not so interesting this way. Does it work if you write A [AR1,P#0.0] ? (without specifying area in command)? |
3/20/2009 9:17 AM | |
Posts: 557 Rating: (64) |
Dear Aret, i have not written A [AR1,P#0.0] ? i have written A M [AR1,P#0.0] Plese find the attach, which will give you a online help. by using this i would like to give you a one example. DB1=ALARM DB DB2=i required to latch like ADB1.DBX0.0 S DB2.DBX0.0 - - -- ADB1.DBX10.0 S DB2.DBX10.0 HERE EXAMPLE L MD0 //COUNTER WHICH WILL INCREMENT P#0.0 L DW#16#80000000 // P AREA +D T MD4 LAR1 // HERE you will get p#0.0 to p#10.0 by incrementing the counter OPN DB1 A DBX [AR1,P#0.0] OPN DB2 S DBX []AR1,P#0.0] SO DB1 WILL MAP WITH DB2 BY INCREMENTING COUNTER . regards AttachmentOnline.zip (379 Downloads) |
3/20/2009 11:31 AM | |
Joined: 1/4/2008 Last visit: 9/2/2024 Posts: 703 Rating: (96) |
Hello, I'm pretty sure that Aret knows this. He would like to know if it works as area-crossing indirect addressing (A [AR1,P#0.0]). When it's used as A M [AR1,P#0.0] it means area-internal indirect addressing. It willaccess directly M area and the area ID inside the pointer is omitted. I've never used indirect addressing of periphery but at least it couldn't be used as first code example, because it's bit access which is impossible in the case of periphery.What seems strange to me is that there isn't specification if it should be input or output, because the address number could be the same for both. Regards Sydney |
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3/20/2009 12:23 PM | |
Posts: 557 Rating: (64) |
Dear Sydney, when we use L DW#16#8000001 LAR1 A [AR1,P#0.0] PLC show system fault, programming error. I think this code is only pointing P#0.0 IF YOU PUT ACCU1 L DW#16#80000000 LAR1 P 0.0 L DW#16#80000001 LAR1 P 0.1 I have develop some code by using Input & output sigmal, it seemok. find the attached online code.& you can also check on simatic manager & tell me your Observation.if you have a different Observation about indirect addressing.......... ..regards Attachmentprogram code.zip (286 Downloads) |
3/20/2009 1:42 PM | |
Joined: 1/4/2008 Last visit: 9/2/2024 Posts: 703 Rating: (96) |
Hello, the fault is because it means the bit acces to periphery which isn't allowed as I wrote. I haven't discussed the pointer loading, but its using. I see the pointing to P area on specified address, but then you use the area-internal indirect addressing which means that the area IDfrom the pointerisn't took into account, you use just address number, not the P area. The result will be the same if you'll load just 0 and 7 to the address register. Regards Sydney |
Last edited by: Sydney at: 3/20/2009 1:45 PM |
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3/20/2009 1:52 PM | |
Posts: 2348 Rating: (264) |
Sidney is right - periphery couldn't be accessedby bits :^) Ok, How about L W#16#80000000 LAR1 L W[AR1,P#0.0] Unfortunalety don't have access to PLC at the moment - can't check by myself. As for Sydney's question on how to distinguish input ant output periphery i heard following explanation: in old S7 CPUs (i guess talk was about S7-300) I and Q areas were mutually exclusive by adresses - i mean if you assign I0.0..I1.7 then you couldn't use Q0.0..Q1.7 - HW Konfig just doesn't allow such addressing... Can't really say if it's true. |
3/20/2009 2:17 PM | |
Joined: 1/4/2008 Last visit: 9/2/2024 Posts: 703 Rating: (96) |
I also don't have any PLC right now and think that this isn't for testing in PLCSIM. Concerning the addressing, I don't think it was exactly as you said, I know that few years ago if the HWconfig editor assigns the addresses then it was like your description, but if you unchecked the system address selection it could beassigned manualy the same address. But I'm not as old to remember the first S7 PLCs so it's possible. What I'm thinking about is that ifthe pointer to P area is used it would depend on using, when you use load instruction it accesses the peripheral inputs and so. Hmm, I have to get some PLC somewhere to test it otherwise I wont sleep well . Regards Sydney |
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3/20/2009 2:59 PM | |
Joined: 1/4/2008 Last visit: 9/2/2024 Posts: 703 Rating: (96) |
ok guys, puzzle solved... L IB 0 |
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3/20/2009 8:25 PM | |
Posts: 2661 Rating: (279) |
Hi Eastern, I think you are confusing the "P" from periphery I/O area and the "P" in P#0.0 for pointer... The periphery I/O area is the "original" address space used by the I/O modules to read/write their status. From this areathe process image partition areas (IW/QW etc.) are derived. Bit addressing is not possible inthe periphery I/O area. Aret &Sidney, The area coding in the area pointer for bothinput and output peripheral areas is 0 (bits 24, 25, 26). The processor decides whether it is I or O depending on whether the statement is L(oad) or T(ransfer)! Thismethodology has its roots in S5 (after all S7 is an extension of S5).
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3/21/2009 3:56 PM | |
Posts: 557 Rating: (64) |
HI All, case 1:- L DW#16#80000000 LAR1 L B [AR1,P#0.0] // IB0 |
Last edited by: Eastern at: 3/21/2009 4:00 PM |
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3/21/2009 9:30 PM | |||||||||||||
Posts: 2661 Rating: (279) |
Hi Eastern,
The case 1 is L PIB 0 / T PQB 0 and not L IB0 / T QB 0 as you stated. The difference between PIW & IW (and PQW & QW) is as follows: PIW is a area in the memory in the CPU where input modules write their status periodically. Similarly PQW is a area in the CPU memory from which the output modules areupdated periodically. Now, there is one more area in the memory called the process image. As the name suggests, process image is a mirror image of PIW & PQW and is addressed using IW and QW. It is the job of the system program inside the CPU to cyclically update the process image area. That is, at thebeginning of every cycle the system program copies the PIW(periphery) to IW(process image inputs) and at the end of every cycle the system program copies the QW(process image outputs) to PQW(periphery).See following diagram:
The advantage of this concept is, the user has the flexibility to set the scan rate. The cycle I mentioned above is OB1, the default (or free) cycle. The free cycle is started as soon as the CPU goes to run mode and is processed again and again till the CPU enters stop mode. With the process image concept, portions of I/O memory can be scanned/updated faster or slower as needed. For example IW0 to IW20 can be updated at OB35 = PIP1 = 100 ms and IW22 to IW50 can be updated at OB37 = PIP2 = 10ms. PIP means Process Image Partition. These settings are done in the CPU properties in HW config. Most S7-400 CPU's and some higher end S7-300 CPU's allow these settings. I suggest you get hold of the following classic book: "Automating with STEP 7 in STL and SCL" by Hans Berger.
The L is local stack of a block and the V is local stack of the previous block. For the general user these areas are not much useful... Regards |
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Last edited by: Phantom75 at: 3/21/2009 10:45 PMAdded ref about Hans Berger |
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3/22/2009 6:01 AM | |
Posts: 557 Rating: (64) |
hi Phantom excellent answer.......... i have small confusion.... example OB1...........Suppose scan time 50ms so each & every 50 ms process image input & output will update............ now if i have network 1...........100.......full from logic...........then what is a difference between to 2 cases which are i am discribing below......... case 1.... OB1:. network 1 L 100 T PQW 512-----------Udate to module ???????? - - - - network 45 L 200 T PQW 512--------------again Udate to module ???????? case 2.... OB1:. network 1 L 100 T QW 512--------------wait till ot complet the scan....... - --------------------n/w1 to n/w44 value will be 100 after that - - network 45 L 200 T QW 512------------new value update & after complete the scan 200 will transfer to module......... is it a PLC uderstanding,please put your expert comment. regards |
3/22/2009 9:00 AM | |
Posts: 2661 Rating: (279) |
Hi Eastern, In case 1 the PQW512 will be updated twice, once in network 1 and again in network 45. And in case 2 the PQW 512 will be 200, it will never see 100. QW 512 will be 100 between network 1 and 45 but the ouput modules will only have the last value 200. Regards |
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