Hello everyone!

How does APL VlvL block status3.bit12 know the upstream interlock is bypassed? The case is I linked interlock08 to VlvL block, when I bypass one of the active interlocks, that means no matter for the output value or output status is same with before, the status3.bit12 of VlvL block changed to true. How is this achieved? Dose anybody have the source code of VlvL?

This is described in the APL manual and standard for all blocks with interlocks.  Essentially the status is calculated based on the signal state and status byte of the interlock input.  You can check the relevant sections for example: 

SIMATIC PCS 7 Advanced Process Library (V10.0) : VlvL standard view : section 4

SIMATIC PCS 7 Advanced Process Library (V10.0) : Forming the group status for interlock information