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| 8/17/2010 2:06 PM | |
Joined: 10/7/2005 Last visit: 11/6/2024 Posts: 3026 Rating:
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Hello XC35 I presume you are dealing with a 115U PLC (CPU 941,2,3 or 4), is this correct? If soRAM memory address E400hex is where the so called DB Address list starts and the following applies (see CPUmanual for more on this): E400/E401: contains current start address of DB0 E402/E403: contains current start address of DB1 E5FE/E5FF: contains current start address of DB255
L KH E400 // DB Address list start address DO DW 12 // "Index" value (5) L DL 0// Load high byte of DW 5(i.e. load a value of 03 into accu1) SLW 1// multiply with two (to accomodate DB address list structure) +F // accu1 now contains E406hex (i.e. poin to address entry of DB 3 in DB address list) LIR 0 // load accu1 with the value that is in address E406hex (i.e. accu1 now holds the current absolute(RAM) address of DW0 of DB 3, NOT the contents of DW0) L KF +1 +F // add 1 to it (i.e. its now the address of DW1 of DB 3) T DW 15 // store this address in DW 15 of currently open DB I'd say that when you stated "I think it is getting data block offset start address" you may very have been right on the money and I hope the above explanation sheds some light on this (and I hope I got it right, it's been a while since I last actively LIR'ed and TIR'ed in S5's). |
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| 8/18/2010 5:15 PM | |
Joined: 8/17/2010 Last visit: 7/25/2024 Posts: 3 Rating:
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Yes it is 944B CPU. Thanks for the explanation. I got it.
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