Usage difference for edge triggers

My first time posting here and rather than start a new thread I hoped it might fit in here with a previous query. 

I've a piece of ladder logic in Step 7 classic using positive edge instruction to call a screen. 
It worked pretty reliably but occasionally would not detect the positive edge (see attached). 
The logic has since been migrated to TIA 17 and on reading the help file for the P_Trig function in TIA 17, I note that it has clear instruction regarding the 'edge memory bit': "The memory area of the edge memory bit has to be located in a DB (Static area for FB) or in the bit memory area"

The help instruction in step 7 classic is not as comprehensive in that it seems I don't need to declare an edge memory bit. 

I've put all the detail on the logic and help files into the attachment.  

Can anyone advise if there are known shortcomings in the way in which the edge detection in the original Step 7 piece of logic is written? (I've seen other instances in step 7 classic where a bool from a DB is used instead of a memory bit but equally I haven't found that to be 100% reliable either)

I have some similar positive edge detection requirements in step 7 classic and want to have confidence I can set it up to work 100% reliably. 

I'd greatly appreciate any help that can be sent my way

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Split from Positive Edge doesn't work anymore?.

smccandl

My first time posting here and rather than start a new thread I hoped it might fit in here with a previous query. 

I've a piece of ladder logic in Step 7 classic using positive edge instruction to call a screen. 
It worked pretty reliably but occasionally would not detect the positive edge (see attached). 
The logic has since been migrated to TIA 17 and on reading the help file for the P_Trig function in TIA 17, I note that it has clear instruction regarding the 'edge memory bit': "The memory area of the edge memory bit has to be located in a DB (Static area for FB) or in the bit memory area"

The help instruction in step 7 classic is not as comprehensive in that it seems I don't need to declare an edge memory bit. 

I've put all the detail on the logic and help files into the attachment.  

Can anyone advise if there are known shortcomings in the way in which the edge detection in the original Step 7 piece of logic is written? (I've seen other instances in step 7 classic where a bool from a DB is used instead of a memory bit but equally I haven't found that to be 100% reliable either)

I have some similar positive edge detection requirements in step 7 classic and want to have confidence I can set it up to work 100% reliably. 

I'd greatly appreciate any help that can be sent my way

The two pieces of code (Classic vs TIAP) is not the same. Then it is also not clear what you find as reliable.

The Step7 Classic code will have the edge trigger evaluate the AND of the two inputs. Step7 (TIAP) evaluates only one signal. The in-software help that you have in the capture is the equivalent of what was used in Step7 Classic.

Network 1
    A     B                    C
---| |---| |---[ P-TRIGE ]----( )
                   M1 

Network 2
    A     B                    C
---| |---|P|------------------( )
          M2

Equivalent in SCL 

Network 1

C := A and B and not M1;

M1 := A and B;


Network 2

C := A and B and not M2;

M1 := B;

smccandl

My first time posting here and rather than start a new thread I hoped it might fit in here with a previous query. 

I've a piece of ladder logic in Step 7 classic using positive edge instruction to call a screen. 
It worked pretty reliably but occasionally would not detect the positive edge (see attached). 
The logic has since been migrated to TIA 17 and on reading the help file for the P_Trig function in TIA 17, I note that it has clear instruction regarding the 'edge memory bit': "The memory area of the edge memory bit has to be located in a DB (Static area for FB) or in the bit memory area"

The help instruction in step 7 classic is not as comprehensive in that it seems I don't need to declare an edge memory bit. 

I've put all the detail on the logic and help files into the attachment.  

Can anyone advise if there are known shortcomings in the way in which the edge detection in the original Step 7 piece of logic is written? (I've seen other instances in step 7 classic where a bool from a DB is used instead of a memory bit but equally I haven't found that to be 100% reliable either)

I have some similar positive edge detection requirements in step 7 classic and want to have confidence I can set it up to work 100% reliably. 

I'd greatly appreciate any help that can be sent my way

------------------------------------------------------------------------------------------
Split from Positive Edge doesn't work anymore?.

// Declare the edge memory bit 
M8000: BOOL;  
// Debounce the input signal 
DIB 100, I0.0, Q0.0;  
// Positive edge detection 
P_Trig M8000, Q0.0, Q1.0;  
// Reset the edge memory bit after each positive edge is detected 
RESET M8000, Q1.0;